High-bandwidth memory (HBM)

High-bandwidth memory is a class of stacked dynamic random-access memory that supplies very high data throughput to processors across a wide interface. It is a distinct strategic control point because advanced artificial-intelligence accelerators require both compute capacity and rapid access to large volumes of data.

Technology

HBM stacks multiple memory dies, connects them through vertical interconnects, and integrates the stack close to a processor through advanced packaging. Performance depends on memory bandwidth, capacity, energy use, thermal management, yield and reliable bonding. A nominal memory chip is not interchangeable with a qualified HBM stack designed for a particular accelerator package.

Production combines advanced DRAM fabrication with stacking, testing and packaging. Leading supply is concentrated among SK hynix, Samsung Electronics and Micron Technology. Accelerator designers and packaging providers must qualify specific products, making rapid substitution difficult even when another supplier has nominal capacity.

Packaging and advanced packaging (CoWoS) is complementary. A shortage of packaging capacity can restrict complete accelerator output even if memory dies and processors exist. Conversely, an advanced processor without suitable HBM may operate below its intended capability.

Export-control status

The United States added HBM controls in its December 2024 semiconductor rule, using technical parameters that capture specified advanced memory. The Export Administration Regulations allocate controls, licence requirements, exceptions and end-use restrictions across Parts 740, 742, 744 and the Commerce Control List in Part 774. Applicability depends on classification, destination, end user, end use and foreign-produced-item rules.

This measure extended United States advanced-computing and semiconductor controls on China (2022-present) beyond visible accelerator chips such as AI accelerators and GPUs (Nvidia H100, A100, and the export-tuned H20). It sought to constrain the memory layer required for advanced systems. The Semiconductor chokepoint therefore comprises a chain of equipment, fabrication, memory, packaging, software and integration controls rather than a single product ban.

Strategic assessment

HBM has high denial value where leading performance cannot be replaced by conventional memory without redesign, lower throughput or higher power demand. Its control also creates incentives for stockpiling, domestic development, diversion and technical adaptation. Controls can delay capability while simultaneously accelerating investment in substitutes.

As at 30 July 2026, analysis should specify the HBM generation or technical threshold, producer, package, accelerator, jurisdiction and relevant export-control provision. Market forecasts and company claims should not be treated as official evidence of production share or effective denial. The strategic question is whether the target can acquire, integrate and sustain enough qualified memory for the intended computing workload.

Control implementation

Enforcement must follow the complete route from producer to integrator and end user. Distributor screening, package identifiers, licence conditions and post-shipment records can expose diversion, but commodity movement through intermediaries limits certainty. A technical threshold also ages as memory generations improve, requiring rule updates if the policy objective remains tied to available computing capability.

Industrial response is equally important. Producers allocate scarce capital across conventional DRAM and HBM, while accelerator firms redesign interfaces around available memory. A control can therefore shift product mix and supplier incentives across allied markets. Measuring success requires evidence of target capability, cost and delay, not merely the nominal volume subject to licensing.

Sources

1. US Department of Commerce, December 2024 semiconductor controls, including HBM.
2. US Export Administration Regulations, Part 740, Licence Exceptions (accessed 30 July 2026).
3. US Export Administration Regulations, Part 742, Control Policy (accessed 30 July 2026).
4. US Export Administration Regulations, Part 744, End-Use and End-User Controls (accessed 30 July 2026).
5. US Export Administration Regulations, Part 774, Commerce Control List (accessed 30 July 2026).